搜索资源列表
sequencecontroller
- this is source code in verilog for sequence controller and clock generator which is used in RISC cpu
risc8
- 8 bit risc code with verilog
risc8
- 基于verilog的8位risc-cpu源码，modelsim仿真-Verilog-based 8-bit risc-cpu source, modelsim simulation
sparc_verilog
- open risc微处理器的verilog源码。基于sparc架构，可以直接综合。适合cpu的学习-open risc microprocessor verilog source. Based on sparc architecture can be directly integrated. Learning for the cpu
risc_mod
- RISC controller code in verilog working code-RISC controller code in verilog working code--VVV
8_RISC_CPU
- risc-cpu，简单的cpu设计,强大的功能简洁的设计，精简化-verilog risc_cpu
clk_gen.v
- 时钟发生器，用计数器功能编写的，能更好的潜入模块中,risc-cpu的一部分-clk_gen verilog
risc_cpu-OK
- 夏宇闻 verilog数字系统设计教程源码 第二版，实现了简单的RISC CPU。印刷版有误，已改正。- A simple RISC CPU Verilog HDL source code. Work well.
BuildingPaPRISCPSystemPinPanPFPGA
- 一个32位 RISC CPU 核心，由Verilog 编写而成-A 32-bit RISC CPU core, written by Verilog
ASSIGNMENT3
- Implementation of risc processor program in verilog coding.-Implementation of risc processor program in verilog coding.
all_cpu
- 精简指令集CPU，可完成移位，跳转等简单功能，适用于FPGA学习，本代码使用verilog编写。-RISC CPU, to be completed by the shift, jumps and other simple functions for FPGA learning to write the code using verilog.
DLX_verilog
- DLX指令集RISC CPU verilog源码，使用哈佛结构可实现十多种指令-DLX instruction set RISC CPU verilog source code, using the Harvard architecture can achieve more than ten kinds of instruction
risc64
- Risc 64 - Bit Verilog Code
openfire_core_latest.tar
- openfire实现 microblaze机构的cpu代码,RISC CPU 的Verilog 设计源码，可综合。内含详细的设计文挡-openfire complete microblaze architecture cpu,RISC CPU Verilog sourcecode and documents
risc8
- 八位简易risccPU，采用verilog描述，FPGA实现-8bit risc CPU
RISC_CPU
- RISC cpu设计，verilog语言，PIC14位指令集-RISC cpu design, verilog language, PIC14-bit instruction set
cpu
- 一份精简指令cpu源代码，用verilog编写，已经通过仿真验证，可以模块化移植。-This is a file of cpu code. The cpu is risc cpu. It is simulated and verificated.And the cpu can be transplanted as a module.
Risc128
- 128 bit RISC processor implementation in verilog